"All these transistors house two full independent cores, each of them 2-way multithreaded as well, for 4 logical CPUs per chip. Each core has 120 each rename registers for integer and for FP, 8 execution units and up to 5 instructions/cycle and 4 FLOPs/cycle issuing throughput, as well as I-cache of 64 KB (2-way set associative) and D-cache (32 KB, 4-way set associative). They share an ultrafast three-bank L2 Cache of 1.92 MB (3 x 640 KB caches with independent buses, 10-way set associative). Its precise bandwidth figure is not known, but should be well above 200 GB/s total. The cores also have enhanced data stream prefetching to make better use of that bandwidth.
"To help feed all these resources, and scale well up to a 64-way real SMP (or 128-way logical SMP with multithreading), POWER5 further improves on the buses towards the outside: besides the two ring buses for its neighbours on the same MCM, which now operate at full processor speed (hey, 2 GHz 256-bit bus is something to cheer about, even if it is actually two 128-bit unidirectional links!), as well as separate half-speed links to the CPUs on the opposite "book", then the other MCMs outside the book, as well as L3 cache bus, then the memory interface (DDR memory controller is on chip now!), and a GX+ I/O bus, a dedicated 6+ GB/s I/O link. The L3 and memory buses are now separate, and, while not confirmed, expect the memory bus to be at least 50% faster than on the POWER4+, i.e. something like 20++ GB/s bandwidth per chip."
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